Commonly assigned Japanese Patent Application No. 2001-206165 filed on Jul. 6, 2001, is incorporated by reference into the present patent application.
1. Field of the Invention
The present invention relates to a GaAs-based semiconductor field-effect transistor.
2. Description of the Related Art
In manufacturing a GaAs-based field effect transistor (FET), after forming source and drain electrodes and a recess in an active layer of GaAs, a gate metal is deposited using a photoresist mask. The photoresist mask has an aperture at a central portion of the recess. Excess metal on the photoresist mask and the mask are lifted off to create a gate electrode. Then, a passivation film is deposited, completing manufacture of a GaAs field-effect transistor. When the lift-off method is used, after removal of the photoresist, residues of the photoresist are completely eliminated by ashing with an oxygen plasma or photo-ozone. Further, in the GaAs field-effect transistor, trapping and releasing of electrons attributed to the surface (interface) states of GaAs gives rise to a gate lag phenomenon (a pulse delay) of the transistor (See xe2x80x9cHideaki IKOMA, Applied Physics, 69 (2000) p.159xe2x80x9d).
Noting this, various methods have been tried to avoid influences of the surface (interface) states at the recess in the surface of the GaAs active layer. For instance, the following attempts have been proposed: suppressing trapping and releasing of electrons at and to the surface states of GaAs through a surface modification treatment, using ammonium sulfide or a nitrogen plasma, applied to the GaAs surface; burying the gate electrode in the recess (i.e., a GaAs-based field-effect transistor with a buried gate structure); and a two-step recess structure (a two-step recess transistor), such as generally denoted at the reference numeral 500 in FIG. 7.
In the two-step recess transistor 500, a GaAs buffer layer 502, a GaAs active layer 503 and a GaAs contact layer 504 are successively disposed on a GaAs semi-insulating substrate 501. A two-step recess 505 is formed in the GaAs active layer 503, and a gate electrode 506 is disposed at the center of the two-step recess 505. Further, source and drain electrodes 507 are formed on the GaAs contact layer 504 on opposite sides of the gate electrode 506. In addition, a passivation film 508 of SiN is deposited to protect the surface.
In the two-step recess transistor 500, it is possible to reduce the width of the recess, in effect, in the vicinity of the gate electrode, reduce trapping and releasing of electrons in the surface states of GaAs on the surface depletion layer, which expands and contracts, in response to the gate-bias (Vg) supplied to the gate electrode, thereby lessening the pulse delay.
However, the two-step recess transistor 500 requires complicated manufacturing processes, causing a decrease in yield. Further, the gate-drain breakdown voltage decreases since the recess width becomes narrower, in effect, in the vicinity of the gate electrode.
The inventor has found that the pulse delay phenomenon is not attributable to trapping and releasing of electrons in surface (interface) states of GaAs, but is due to leakage currents in the vicinity of a GaAs oxide layer formed on the surface of the recess in the ashing step after the lift-off step. The inventor found that the leakage currents (changes in quantities of electrons) in the GaAs oxide layer contributes to changes in surface depletion layer thickness, gate lag, and gate-drain breakdown voltage, etc.
In other words, the conventional two-step recess transistor has a narrower width recess, in effect, thereby reducing the influence of the GaAs oxide layer formed on the surface of the recess.
The present invention relates to GaAs-based field-effect transistors, and improved performance, such as a reduction in gate-lag, controllability of gate breakdown voltage, and improvement in noise characteristics.
The inventor found that the gate-lag effect is reduced when the thickness of the GaAs oxide layer between the surface of GaAs and the passivation film is reduced. The thickness of the GaAs oxide layer is ensured to be approximately equal to the lattice constant of a GaAs-based semiconductor material if the effectiveness of photoresist removal in a lift-off process is sufficiently improved to eliminate the ashing step. Further, as the effectiveness of photoresist removal in the lift-off process is improved and the ashing step is eliminated without adversely influencing transistor performances, various characteristics of a transistor, such as controllability of gate-drain breakdown voltage and noise characteristics improve.
More specifically, photoresist removers containing N-methyl-2-pyrrolidone (NMP) as a component make it possible to completely remove residues of photoresists to such an extent as to omit the following ashing step from the lift-off process. Accordingly, it is possible to control the thickness of a GaAs oxide layer produced as side effect in the ashing step, so the thickness of the GaAs oxide layer is approximately equal to the lattice constant of GaAs. Hence, the device performance of GaAs FETs is improved. This point of view has led the present invention.
JP 10-335352 discloses that a reduction of the pulse delay (gate-lag) occurs when the thickness of a GaAs oxide layer is 20 xc3x85 or thinner. However, the present invention reveals the realities of further improvement of various characteristics of transistors, such as controllability of gate breakdown voltages and noise as well as further reduction of the pulse delay, provided that the thickness of the GaAs oxide layer is limited to be in the approximate range of the lattice constant of GaAs.
In other words, the present invention is directed to a GaAs-based semiconductor field-effect transistor in which electrons flowing from a source electrode to a drain electrode are controlled by means of a signal supplied to a gate electrode. The transistor comprises n-doped GaAs-based semiconductor materials. A source electrode and a drain electrode are formed on an active layer of a GaAs-based semiconductor material. A gate electrode is formed on the active layer between the source electrode and the drain electrode. The thickness of the GaAs oxide layer on the active layer is approximately equal to the lattice constant of the GaAs-based semiconductor material. The thickness of the oxide layer, the thickness of the GaAs native oxide layer, is preferably about 4 through 6 xc3x85, and more preferably about 5 xc3x85, which is the approximate range of the lattice constant of GaAs and GaAs-based semiconductor materials.